64ch FPIX

We helped KEK with their FPIX project. This is a board developed by KEK’s Detector Project Office  to collect signals from Si-APD chips. The signal is sampled at 0.5ns by the FPGA and histogrammed within the FPGA. The created histogram is transferred to the PC using SiTCP. In order to efficiently dissipate heat from the FPGA, etc., most of the components are placed on the bottom, and the structure is such that a heat dissipation aluminum block is placed on the bottom.